1. Technical Field
The present invention relates to estimating power consumption in processor cores, and more particularly, to estimating power consumption when processing different workloads.
2. Discussion of the Related Art
There are a number of ways of estimating power consumption in processor cores executing different workloads. Existing solutions range from carrying out power analysis at the architecture level, which is less accurate, to detailed analysis at the gate/circuit level, which is more, accurate, but complex and time consuming.
Architecture level power analysis tools use simulators that can run various workloads relatively quickly. Nevertheless, these tools rely on estimates for power in different parts of the processor core (either based on guesses, approximations, or from detailed analysis of gate/circuit level implementation) to put together an overall power estimate. For many processor cores, however, the various parts that make up the core cannot be easily broken down into independent units for which detailed power characterization can be obtained.
Gate/circuit level analysis requires detailed gate level or circuit level simulations, using a power analysis tool for each workload of interest. Examples of such power simulators are PowerTheater® from Sequence Design, Inc. that can do power analysis at the gate level, or PowerMill® (now known as NanoSim®) from Synopsys, Inc. and PowerSpice® that can do power analysis at the circuit level. These existing solutions are time consuming. They need to be rerun for every new workload. More seriously, they are not feasible for use with long-running workloads, either because the analysis takes very long to finish or because the tools fail during such long simulations due to the complexity of the analysis. Thus, such tools are useful only for relatively small code sequences, generally no more than several hundred instructions, which may be just a small part of the entire workload. These limitations make such power analysis tools unattractive for making quick power estimations for various workloads.
Therefore, there is the need for a methodology that will allow power comparisons to be done quickly for different workloads. This methodology also needs to be applicable to processor cores that cannot be broken into units for individual power analysis, for use with existing architecture level power analysis methodologies.